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#REDIRECT [[CYCLES.TXT/fr]]
 +
{{Languages|CYCLES.TXT}}
  +
<pre>
  +
SHIZUKA is pleased to present this 68000 cycle table
  +
created in two evening sessions with the valuable help of:
  +
  +
craft2 (stedi)
  +
hard drive (wow, the speed)
  +
"68000 instruction guide, vol 2 by NACHTMANN at PUBLITRONIC"
  +
  +
please distribute this table without modifying the header
  +
  +
effective address calculation
  +
  +
b/w l
  +
  +
dn 0 0
  +
an 0 0
  +
(an) 4 8
  +
(an)+ 4 8
  +
-(an) 6 10
  +
d16(an) 8 12
  +
d8(an,xi) 10 14
  +
abs.w 8 12
  +
abs.l 12 16
  +
d16(pc) 8 12
  +
d8(pc,x1) 10 14
  +
imm 4 8
  +
  +
  +
move.b and move.w
  +
  +
dn an (an) (an)+ -(an) d16(an) d8(an,xi) abs.w abs.l
  +
dn 4 4 8 8 8 12 14 12 16
  +
an 4 4 8 8 8 12 14 12 16
  +
(an) 8 8 12 12 12 16 18 16 20
  +
(an)+ 8 8 12 12 12 16 18 16 20
  +
-(an) 10 10 14 14 14 18 20 18 22
  +
d16(an) 12 12 16 16 16 20 22 20 24
  +
d8(an,xi) 14 14 18 18 18 22 24 22 26
  +
abs.w 12 12 16 16 16 20 22 20 24
  +
abs.l 16 16 20 20 20 24 26 24 28
  +
d16(pc) 12 12 16 16 16 20 22 20 24
  +
d8(pc,x1) 14 14 18 18 18 22 24 22 26
  +
imm 8 8 12 12 12 16 18 16 20
  +
  +
move.l
  +
  +
dn an (an) (an)+ -(an) d16(an) d8(an,xi) abs.w abs.l
  +
dn 4 4 12 12 12 16 18 16 20
  +
an 4 4 12 12 12 16 18 16 20
  +
(an) 12 12 20 20 20 24 26 24 28
  +
(an)+ 12 12 20 20 20 24 26 24 28
  +
-(an) 14 14 22 22 22 26 28 26 30
  +
d16(an) 16 16 24 24 24 28 30 28 32
  +
d8(an,xi) 18 18 26 26 26 30 32 30 34
  +
abs.w 16 16 24 24 24 28 30 28 32
  +
abs.l 20 20 28 28 28 32 34 32 36
  +
d16(pc) 16 16 24 24 24 28 30 28 32
  +
d8(pc,x1) 18 18 26 26 26 30 32 30 34
  +
imm 12 12 20 20 20 24 26 24 28
  +
  +
  +
  +
op(ea),an op(ea),dn op dn,(m)
  +
  +
add.b - 4+ 8+
  +
add.w 8+ 4+ 8+
  +
add.l 6+& 6+& 12+
  +
and.b - 4+ 8+
  +
and.w - 4+ 8+
  +
and.l - 6+& 12+
  +
cmp.b - 4+ -
  +
cmp.w 6+ 4+ -
  +
cmp.l 6+ 6+ -
  +
divs - 158+* -
  +
divu - 140+* -
  +
eor.b - 4+ 8+
  +
eor.w - 4+ 8+
  +
eor.l - 8+ 12+
  +
muls - 70+* -
  +
mulu - 70+* -
  +
or.b - 4+ 8+
  +
or.w - 4+ 8+
  +
or.l - 6+& 12+
  +
sub.b - 4+ 8+
  +
sub.w 8+ 4+ 8+
  +
sub.l 6+& 6+& 12+
  +
  +
  +
  +
+ = add the time for calculating the effective address
  +
& = add 2 clock cycles for modes an dn and immediate
  +
* = maximum duration
  +
  +
  +
op #,dn op #,an op #,m
  +
  +
addi.b 8 - 12+
  +
addi.w 8 - 12+
  +
addi.l 16 - 20+
  +
addq.b 4 - 8+
  +
addq.w 4 8 8+
  +
addq.l 8 8 12+
  +
andi.b 8 - 12+
  +
andi.w 8 - 12+
  +
andi.l 16 - 20+
  +
cmpi.b 8 - 8+
  +
cmpi.w 8 - 8+
  +
cmpi.l 14 - 12+
  +
eori.b 8 - 12+
  +
eori.w 8 - 12+
  +
eori.l 16 - 20+
  +
moveq 4 - -
  +
ori.b 8 - 12+
  +
ori.w 8 - 12+
  +
ori.l 16 - 20+
  +
subi.b 8 - 12+
  +
subi.w 8 - 12+
  +
subi.l 16 - 20+
  +
subq.b 4 - 8+
  +
subq.w 4 8 8+
  +
subq.l 8 8 12+
  +
  +
+ = add the time for calculating the effective address
  +
  +
  +
register memory
  +
  +
clr.b 4 8+
  +
clr.w 4 8+
  +
clr.l 6 12+
  +
nbcd 6 8+
  +
neg.b 4 8+
  +
neg.w 4 8+
  +
neg.l 6 12+
  +
negx.b 4 8+
  +
negx.w 4 8+
  +
negx.l 6 12+
  +
not.b 4 8+
  +
not.w 4 8+
  +
not.l 6 12+
  +
scc (cc=0) 4 8+
  +
scc (cc=1) 6 8+
  +
tas 4 10+
  +
tst.b 4 4+
  +
tst.w 4 4+
  +
tst.l 4 4+
  +
  +
+ = add the time for calculating the effective address
  +
  +
  +
registers memory
  +
  +
asr.b & asl.b 6+2n
  +
asr.w & asl.w 6+2n 8+
  +
asr.l & asl.l 8+2n
  +
lsr.b & lsl.b 6+2n
  +
lsr.w & lsl.w 6+2n 8+
  +
lsr.l & lsl.l 8+2n
  +
ror.b & rol.b 6+2n
  +
ror.w & rol.w 6+2n 8+
  +
ror.l & rol.l 8+2n
  +
roxr.b & roxl.b 6+2n
  +
roxr.w & roxl.w 6+2n 8+
  +
roxr.l & roxl.l 8+2n
  +
  +
+ = add the time for calculating the effective address
  +
n is the number of successive rotations or shifts
  +
  +
dynamic dynamic static static
  +
register memory register memory
  +
  +
bchg.b - 8+ - 12+
  +
bchg.l 8* - 12* -
  +
bclr.b - 8+ - 12+
  +
bclr.l 10* - 14* -
  +
bset.b - 8+ - 12+
  +
bset.l 8* - 12* -
  +
btst.b - 4+ - 8+
  +
btst.l 6 - 10 -
  +
  +
  +
+ = add the time for calculating the effective address
  +
* = maximum duration
  +
  +
  +
branching no
  +
executed branching
  +
  +
bcc.s 10 8
  +
bcc.l 10 12
  +
bra.s 10 -
  +
bra.l 10 -
  +
bsr.s 18 -
  +
bsr.l 18 -
  +
dbcc cc=1 - 12
  +
dbcc cc=0 10 14
  +
  +
  +
  +
  +
(an) (an)+ -(an) 16(an) d8(an,xi) abs.w abs.l d16(pc) d8(pc,xi)
  +
  +
jmp 8 - - 10 14 10 12 10 14
  +
jsr 16 - - 18 22 18 20 18 22
  +
lea 4 - - 8 12 8 12 8 12
  +
pea 12 - - 16 20 16 20 16 20
  +
movem.w 12+4n 12+4n - 16+4n 18+4n 16+4n 20+4n 16+4n 18+4n
  +
(m->r)
  +
movem.l 12+8n 12+8n - 16+8n 18+8n 16+8n 20+8n 16+8n 18+8n
  +
(m->r)
  +
movem.w 8+4n - 8+4n 12+4n 14+4n 12+4n 16+4n - -
  +
(r->m)
  +
movem.l 8+8n - 8+8n 12+8n 14+8n 12+8n 16+8n - -
  +
(r->m)
  +
  +
  +
n is the number of register transfers to be performed
  +
  +
  +
op dn,dn op m,m
  +
  +
addx.b 4 18
  +
addx.w 4 18
  +
addx.l 8 30
  +
cmpm.b - 12
  +
cmpm.w - 12
  +
cmpm.l - 20
  +
subx.b 4 18
  +
subx.w 4 18
  +
subx.l 8 30
  +
abcd 6 18
  +
sbcd 6 18
  +
  +
  +
  +
68000 68000
  +
r->m m->r
  +
  +
movep.w 16 16
  +
movep.l 24 24
  +
  +
  +
  +
68000 68000
  +
register memory
  +
  +
andi to ccr 20 -
  +
andi to sr 20 -
  +
chk (without trap) 10 -
  +
eori to ccr 20 -
  +
eori to sr 20 -
  +
exg 6 -
  +
ext 4 -
  +
link 16 -
  +
move to ccr 12 12&
  +
move to sr 12 12&
  +
move from sr 6 8&
  +
move usp 4 -
  +
nop 4 -
  +
ori to ccr 20 -
  +
ori to sr 20 -
  +
reset 132 -
  +
rte 20 -
  +
rtr 20 -
  +
rts 16 -
  +
stop 4 -
  +
swap 4 -
  +
trapv (without trap) 4 -
  +
unlk 12 -
  +
  +
& = add the time for calculating the effective address
  +
  +
  +
68000
  +
  +
address error 50
  +
bus error 50
  +
chk instruction 44+*
  +
illegal instruction 34
  +
interruption 44#
  +
privilege violation 34
  +
trace 34
  +
trap 38
  +
trapvs 34
  +
  +
  +
+ add the time for calculating the effective address
  +
* maximum duration
  +
# 4 clock cycles included for the interruption cycle
  +
  +
  +
</pre>
  +
Back to [[ASM_Tutorial]]
  +
[[Category: 68000 ASSEMBLY ON ATARI ST Part 1 ]]

Latest revision as of 00:02, 17 December 2023

Languages: 

English  • français 

SHIZUKA is pleased to present this 68000 cycle table
created in two evening sessions with the valuable help of:

craft2 (stedi)
hard drive (wow, the speed)
"68000 instruction guide, vol 2 by NACHTMANN at PUBLITRONIC"

please distribute this table without modifying the header

effective address calculation

                b/w     l

dn              0       0
an              0       0
(an)            4       8
(an)+           4       8
-(an)           6       10
d16(an)         8       12
d8(an,xi)       10      14
abs.w           8       12
abs.l           12      16
d16(pc)         8       12
d8(pc,x1)       10      14
imm             4       8


move.b and move.w

            dn   an   (an)   (an)+   -(an)   d16(an)  d8(an,xi)   abs.w   abs.l 
dn           4    4    8      8        8       12       14         12      16
an           4    4    8      8        8       12       14         12      16
(an)         8    8    12     12       12      16       18         16      20
(an)+        8    8    12     12       12      16       18         16      20
-(an)        10   10   14     14       14      18       20         18      22
d16(an)      12   12   16     16       16      20       22         20      24
d8(an,xi)    14   14   18     18       18      22       24         22      26
abs.w        12   12   16     16       16      20       22         20      24
abs.l        16   16   20     20       20      24       26         24      28
d16(pc)      12   12   16     16       16      20       22         20      24
d8(pc,x1)    14   14   18     18       18      22       24         22      26
imm          8    8    12     12       12      16       18         16      20

move.l

            dn   an   (an)   (an)+   -(an)   d16(an)  d8(an,xi)   abs.w   abs.l 
dn           4    4    12     12       12      16       18         16      20
an           4    4    12     12       12      16       18         16      20
(an)         12   12   20     20       20      24       26         24      28
(an)+        12   12   20     20       20      24       26         24      28
-(an)        14   14   22     22       22      26       28         26      30
d16(an)      16   16   24     24       24      28       30         28      32 
d8(an,xi)    18   18   26     26       26      30       32         30      34
abs.w        16   16   24     24       24      28       30         28      32
abs.l        20   20   28     28       28      32       34         32      36
d16(pc)      16   16   24     24       24      28       30         28      32
d8(pc,x1)    18   18   26     26       26      30       32         30      34
imm          12   12   20     20       20      24       26         24      28



                op(ea),an       op(ea),dn       op dn,(m)

add.b           -               4+              8+
add.w           8+              4+              8+
add.l           6+&             6+&             12+
and.b           -               4+              8+
and.w           -               4+              8+
and.l           -               6+&             12+
cmp.b           -               4+              -
cmp.w           6+              4+              -
cmp.l           6+              6+              -
divs            -               158+*           -
divu            -               140+*           -
eor.b           -               4+              8+
eor.w           -               4+              8+
eor.l           -               8+              12+
muls            -               70+*            -
mulu            -               70+*            -
or.b            -               4+              8+
or.w            -               4+              8+
or.l            -               6+&             12+
sub.b           -               4+              8+
sub.w           8+              4+              8+
sub.l           6+&             6+&             12+



+ = add the time for calculating the effective address
& = add 2 clock cycles for modes an dn and immediate
* = maximum duration


                op #,dn         op #,an         op #,m

addi.b          8               -               12+
addi.w          8               -               12+
addi.l          16              -               20+
addq.b          4               -               8+
addq.w          4               8               8+
addq.l          8               8               12+
andi.b          8               -               12+
andi.w          8               -               12+
andi.l          16              -               20+
cmpi.b          8               -               8+
cmpi.w          8               -               8+
cmpi.l          14              -               12+
eori.b          8               -               12+
eori.w          8               -               12+
eori.l          16              -               20+
moveq           4               -               -
ori.b           8               -               12+
ori.w           8               -               12+
ori.l           16              -               20+
subi.b          8               -               12+
subi.w          8               -               12+
subi.l          16              -               20+
subq.b          4               -               8+
subq.w          4               8               8+
subq.l          8               8               12+

+ = add the time for calculating the effective address


                register        memory

clr.b           4               8+
clr.w           4               8+
clr.l           6               12+
nbcd            6               8+
neg.b           4               8+
neg.w           4               8+
neg.l           6               12+
negx.b          4               8+
negx.w          4               8+
negx.l          6               12+
not.b           4               8+
not.w           4               8+
not.l           6               12+
scc (cc=0)      4               8+
scc (cc=1)      6               8+
tas             4               10+
tst.b           4               4+
tst.w           4               4+
tst.l           4               4+

+ = add the time for calculating the effective address


                   registers     memory

asr.b & asl.b    6+2n
asr.w & asl.w    6+2n            8+
asr.l & asl.l    8+2n
lsr.b & lsl.b    6+2n
lsr.w & lsl.w    6+2n            8+
lsr.l & lsl.l    8+2n
ror.b & rol.b    6+2n
ror.w & rol.w    6+2n            8+
ror.l & rol.l    8+2n
roxr.b & roxl.b  6+2n
roxr.w & roxl.w  6+2n            8+
roxr.l & roxl.l  8+2n

+ = add the time for calculating the effective address
n is the number of successive rotations or shifts

          dynamic        dynamic         static           static
          register       memory          register         memory

bchg.b        -            8+              -               12+
bchg.l        8*           -               12*             -
bclr.b        -            8+              -               12+
bclr.l        10*          -               14*             -
bset.b        -            8+              -               12+
bset.l        8*           -               12*             -
btst.b        -            4+              -               8+
btst.l        6            -               10              -


+ = add the time for calculating the effective address
* = maximum duration


              branching        no
              executed         branching

bcc.s              10             8
bcc.l              10             12
bra.s              10             -
bra.l              10             -
bsr.s              18             -
bsr.l              18             -
dbcc cc=1          -              12
dbcc cc=0          10             14




         (an)  (an)+  -(an)   16(an) d8(an,xi)  abs.w  abs.l d16(pc) d8(pc,xi)

jmp        8      -     -       10      14        10      12     10     14      
jsr        16     -     -       18      22        18      20     18     22
lea        4      -     -       8       12        8       12     8      12
pea        12     -     -       16      20        16      20     16     20
movem.w    12+4n  12+4n -       16+4n   18+4n     16+4n   20+4n  16+4n  18+4n
(m->r)       
movem.l    12+8n  12+8n -       16+8n   18+8n     16+8n   20+8n  16+8n  18+8n
(m->r)
movem.w    8+4n   -     8+4n    12+4n   14+4n     12+4n   16+4n  -      -
(r->m)
movem.l    8+8n   -     8+8n     12+8n  14+8n     12+8n   16+8n  -      -
(r->m)


n is the number of register transfers to be performed


             op dn,dn      op m,m

addx.b          4            18
addx.w          4            18
addx.l          8            30
cmpm.b          -            12
cmpm.w          -            12
cmpm.l          -            20
subx.b          4            18
subx.w          4            18
subx.l          8            30
abcd            6            18
sbcd            6            18



                68000           68000
                r->m            m->r

movep.w          16               16
movep.l          24               24



                        68000           68000
                        register        memory

andi to ccr                20              -
andi to sr                 20              -
chk (without trap)         10              -
eori to ccr                20              -
eori to sr                 20              -
exg                        6               -
ext                        4               -
link                       16              -
move to ccr                12              12&
move to sr                 12              12&
move from sr               6               8&
move usp                   4               -
nop                        4               -
ori to ccr                 20              -
ori to sr                  20              -
reset                      132             -
rte                        20              -
rtr                        20              -
rts                        16              -
stop                       4               -
swap                       4               -
trapv (without trap)       4               -
unlk                       12              -

& = add the time for calculating the effective address


                           68000

address error              50
bus error                  50
chk instruction            44+*
illegal instruction        34
interruption               44#
privilege violation        34
trace                      34
trap                       38
trapvs                     34


+ add the time for calculating the effective address
* maximum duration
# 4 clock cycles included for the interruption cycle

Back to ASM_Tutorial

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