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{{Languages|CYCLES.TXT}} |
{{Languages|CYCLES.TXT}} |
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<pre> |
<pre> |
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| − | SHIZUKA is pleased to present this |
+ | SHIZUKA is pleased to present this 68000 cycle table |
| + | created in two evening sessions with the valuable help of: |
||
| − | craft2 ( |
+ | craft2 (stedi) |
| − | hard drive ( |
+ | hard drive (wow, the speed) |
"68000 instruction guide, vol 2 by NACHTMANN at PUBLITRONIC" |
"68000 instruction guide, vol 2 by NACHTMANN at PUBLITRONIC" |
||
| − | + | please distribute this table without modifying the header |
|
| − | + | effective address calculation |
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b/w l |
b/w l |
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| Line 22: | Line 23: | ||
abs.w 8 12 |
abs.w 8 12 |
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abs.l 12 16 |
abs.l 12 16 |
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| − | d16(pc) 8 12 |
+ | d16(pc) 8 12 |
d8(pc,x1) 10 14 |
d8(pc,x1) 10 14 |
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imm 4 8 |
imm 4 8 |
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| − | ... |
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| + | move.b and move.w |
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| − | interruption 44# |
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| + | |||
| − | violation de privilège 34 |
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| − | + | dn an (an) (an)+ -(an) d16(an) d8(an,xi) abs.w abs.l |
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| − | + | dn 4 4 8 8 8 12 14 12 16 |
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| − | + | an 4 4 8 8 8 12 14 12 16 |
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| + | (an) 8 8 12 12 12 16 18 16 20 |
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| + | (an)+ 8 8 12 12 12 16 18 16 20 |
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| + | -(an) 10 10 14 14 14 18 20 18 22 |
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| + | d16(an) 12 12 16 16 16 20 22 20 24 |
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| + | d8(an,xi) 14 14 18 18 18 22 24 22 26 |
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| + | abs.w 12 12 16 16 16 20 22 20 24 |
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| + | abs.l 16 16 20 20 20 24 26 24 28 |
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| + | d16(pc) 12 12 16 16 16 20 22 20 24 |
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| + | d8(pc,x1) 14 14 18 18 18 22 24 22 26 |
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| + | imm 8 8 12 12 12 16 18 16 20 |
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| + | |||
| + | move.l |
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| + | |||
| + | dn an (an) (an)+ -(an) d16(an) d8(an,xi) abs.w abs.l |
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| + | dn 4 4 12 12 12 16 18 16 20 |
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| + | an 4 4 12 12 12 16 18 16 20 |
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| + | (an) 12 12 20 20 20 24 26 24 28 |
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| + | (an)+ 12 12 20 20 20 24 26 24 28 |
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| + | -(an) 14 14 22 22 22 26 28 26 30 |
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| + | d16(an) 16 16 24 24 24 28 30 28 32 |
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| + | d8(an,xi) 18 18 26 26 26 30 32 30 34 |
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| + | abs.w 16 16 24 24 24 28 30 28 32 |
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| + | abs.l 20 20 28 28 28 32 34 32 36 |
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| + | d16(pc) 16 16 24 24 24 28 30 28 32 |
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| + | d8(pc,x1) 18 18 26 26 26 30 32 30 34 |
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| + | imm 12 12 20 20 20 24 26 24 28 |
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| + | |||
| + | |||
| + | |||
| + | op(ea),an op(ea),dn op dn,(m) |
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| + | |||
| + | add.b - 4+ 8+ |
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| + | add.w 8+ 4+ 8+ |
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| + | add.l 6+& 6+& 12+ |
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| + | and.b - 4+ 8+ |
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| + | and.w - 4+ 8+ |
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| + | and.l - 6+& 12+ |
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| + | cmp.b - 4+ - |
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| + | cmp.w 6+ 4+ - |
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| + | cmp.l 6+ 6+ - |
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| + | divs - 158+* - |
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| + | divu - 140+* - |
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| + | eor.b - 4+ 8+ |
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| + | eor.w - 4+ 8+ |
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| + | eor.l - 8+ 12+ |
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| + | muls - 70+* - |
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| + | mulu - 70+* - |
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| + | or.b - 4+ 8+ |
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| + | or.w - 4+ 8+ |
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| + | or.l - 6+& 12+ |
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| + | sub.b - 4+ 8+ |
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| + | sub.w 8+ 4+ 8+ |
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| + | sub.l 6+& 6+& 12+ |
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| + | |||
| + | |||
| + | |||
| + | + = add the time for calculating the effective address |
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| + | & = add 2 clock cycles for modes an dn and immediate |
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| + | * = maximum duration |
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| + | |||
| + | |||
| + | op #,dn op #,an op #,m |
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| + | |||
| + | addi.b 8 - 12+ |
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| + | addi.w 8 - 12+ |
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| + | addi.l 16 - 20+ |
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| + | addq.b 4 - 8+ |
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| + | addq.w 4 8 8+ |
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| + | addq.l 8 8 12+ |
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| + | andi.b 8 - 12+ |
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| + | andi.w 8 - 12+ |
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| + | andi.l 16 - 20+ |
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| + | cmpi.b 8 - 8+ |
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| + | cmpi.w 8 - 8+ |
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| + | cmpi.l 14 - 12+ |
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| + | eori.b 8 - 12+ |
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| + | eori.w 8 - 12+ |
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| + | eori.l 16 - 20+ |
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| + | moveq 4 - - |
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| + | ori.b 8 - 12+ |
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| + | ori.w 8 - 12+ |
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| + | ori.l 16 - 20+ |
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| + | subi.b 8 - 12+ |
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| + | subi.w 8 - 12+ |
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| + | subi.l 16 - 20+ |
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| + | subq.b 4 - 8+ |
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| + | subq.w 4 8 8+ |
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| + | subq.l 8 8 12+ |
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| + | |||
| + | + = add the time for calculating the effective address |
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| + | |||
| + | |||
| + | register memory |
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| + | |||
| + | clr.b 4 8+ |
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| + | clr.w 4 8+ |
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| + | clr.l 6 12+ |
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| + | nbcd 6 8+ |
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| + | neg.b 4 8+ |
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| + | neg.w 4 8+ |
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| + | neg.l 6 12+ |
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| + | negx.b 4 8+ |
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| + | negx.w 4 8+ |
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| + | negx.l 6 12+ |
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| + | not.b 4 8+ |
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| + | not.w 4 8+ |
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| + | not.l 6 12+ |
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| + | scc (cc=0) 4 8+ |
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| + | scc (cc=1) 6 8+ |
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| + | tas 4 10+ |
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| + | tst.b 4 4+ |
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| + | tst.w 4 4+ |
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| + | tst.l 4 4+ |
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| + | |||
| + | + = add the time for calculating the effective address |
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| + | |||
| + | |||
| + | registers memory |
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| + | |||
| + | asr.b & asl.b 6+2n |
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| + | asr.w & asl.w 6+2n 8+ |
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| + | asr.l & asl.l 8+2n |
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| + | lsr.b & lsl.b 6+2n |
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| + | lsr.w & lsl.w 6+2n 8+ |
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| + | lsr.l & lsl.l 8+2n |
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| + | ror.b & rol.b 6+2n |
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| + | ror.w & rol.w 6+2n 8+ |
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| + | ror.l & rol.l 8+2n |
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| + | roxr.b & roxl.b 6+2n |
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| + | roxr.w & roxl.w 6+2n 8+ |
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| + | roxr.l & roxl.l 8+2n |
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| + | |||
| − | + add the effective address calculation time |
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| − | * maximum duration |
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| − | # 4 clock periods included for the interrupt cycle |
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</pre> |
</pre> |
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Revision as of 15:36, 16 December 2023
SHIZUKA is pleased to present this 68000 cycle table
created in two evening sessions with the valuable help of:
craft2 (stedi)
hard drive (wow, the speed)
"68000 instruction guide, vol 2 by NACHTMANN at PUBLITRONIC"
please distribute this table without modifying the header
effective address calculation
b/w l
dn 0 0
an 0 0
(an) 4 8
(an)+ 4 8
-(an) 6 10
d16(an) 8 12
d8(an,xi) 10 14
abs.w 8 12
abs.l 12 16
d16(pc) 8 12
d8(pc,x1) 10 14
imm 4 8
move.b and move.w
dn an (an) (an)+ -(an) d16(an) d8(an,xi) abs.w abs.l
dn 4 4 8 8 8 12 14 12 16
an 4 4 8 8 8 12 14 12 16
(an) 8 8 12 12 12 16 18 16 20
(an)+ 8 8 12 12 12 16 18 16 20
-(an) 10 10 14 14 14 18 20 18 22
d16(an) 12 12 16 16 16 20 22 20 24
d8(an,xi) 14 14 18 18 18 22 24 22 26
abs.w 12 12 16 16 16 20 22 20 24
abs.l 16 16 20 20 20 24 26 24 28
d16(pc) 12 12 16 16 16 20 22 20 24
d8(pc,x1) 14 14 18 18 18 22 24 22 26
imm 8 8 12 12 12 16 18 16 20
move.l
dn an (an) (an)+ -(an) d16(an) d8(an,xi) abs.w abs.l
dn 4 4 12 12 12 16 18 16 20
an 4 4 12 12 12 16 18 16 20
(an) 12 12 20 20 20 24 26 24 28
(an)+ 12 12 20 20 20 24 26 24 28
-(an) 14 14 22 22 22 26 28 26 30
d16(an) 16 16 24 24 24 28 30 28 32
d8(an,xi) 18 18 26 26 26 30 32 30 34
abs.w 16 16 24 24 24 28 30 28 32
abs.l 20 20 28 28 28 32 34 32 36
d16(pc) 16 16 24 24 24 28 30 28 32
d8(pc,x1) 18 18 26 26 26 30 32 30 34
imm 12 12 20 20 20 24 26 24 28
op(ea),an op(ea),dn op dn,(m)
add.b - 4+ 8+
add.w 8+ 4+ 8+
add.l 6+& 6+& 12+
and.b - 4+ 8+
and.w - 4+ 8+
and.l - 6+& 12+
cmp.b - 4+ -
cmp.w 6+ 4+ -
cmp.l 6+ 6+ -
divs - 158+* -
divu - 140+* -
eor.b - 4+ 8+
eor.w - 4+ 8+
eor.l - 8+ 12+
muls - 70+* -
mulu - 70+* -
or.b - 4+ 8+
or.w - 4+ 8+
or.l - 6+& 12+
sub.b - 4+ 8+
sub.w 8+ 4+ 8+
sub.l 6+& 6+& 12+
+ = add the time for calculating the effective address
& = add 2 clock cycles for modes an dn and immediate
* = maximum duration
op #,dn op #,an op #,m
addi.b 8 - 12+
addi.w 8 - 12+
addi.l 16 - 20+
addq.b 4 - 8+
addq.w 4 8 8+
addq.l 8 8 12+
andi.b 8 - 12+
andi.w 8 - 12+
andi.l 16 - 20+
cmpi.b 8 - 8+
cmpi.w 8 - 8+
cmpi.l 14 - 12+
eori.b 8 - 12+
eori.w 8 - 12+
eori.l 16 - 20+
moveq 4 - -
ori.b 8 - 12+
ori.w 8 - 12+
ori.l 16 - 20+
subi.b 8 - 12+
subi.w 8 - 12+
subi.l 16 - 20+
subq.b 4 - 8+
subq.w 4 8 8+
subq.l 8 8 12+
+ = add the time for calculating the effective address
register memory
clr.b 4 8+
clr.w 4 8+
clr.l 6 12+
nbcd 6 8+
neg.b 4 8+
neg.w 4 8+
neg.l 6 12+
negx.b 4 8+
negx.w 4 8+
negx.l 6 12+
not.b 4 8+
not.w 4 8+
not.l 6 12+
scc (cc=0) 4 8+
scc (cc=1) 6 8+
tas 4 10+
tst.b 4 4+
tst.w 4 4+
tst.l 4 4+
+ = add the time for calculating the effective address
registers memory
asr.b & asl.b 6+2n
asr.w & asl.w 6+2n 8+
asr.l & asl.l 8+2n
lsr.b & lsl.b 6+2n
lsr.w & lsl.w 6+2n 8+
lsr.l & lsl.l 8+2n
ror.b & rol.b 6+2n
ror.w & rol.w 6+2n 8+
ror.l & rol.l 8+2n
roxr.b & roxl.b 6+2n
roxr.w & roxl.w 6+2n 8+
roxr.l & roxl.l 8+2n