COURS A.TXT
******************************************************************
* *
* SUPPLEMENTARY COURSE ref. A *
* *
* by The Fierce Rabbit (from 44E) *
* *
* *
******************************************************************
This chapter was added while I was writing the
6th course. It seemed indeed interesting to provide
additional details about the 68000.
This information concerns the pinout of this microprocessor and
may seem superfluous. However, they allow a much better
understanding of various phenomena. Don't worry
if some terms seem hardly comprehensible because we will
refer to this document quite often in the following
courses, which will allow us to get explanations as needed.
The 68000 is composed of a tiny silicon 'chip', to
which wires are connected and, in turn, ended by small
pins (the 'legs'). It is the number of pins that determines
the size of the package, not the size of the silicon die,
which is much smaller.
The 68000's package is approximately 8.2 cm long by 2.3 cm wide
and has 64 pins which we will describe briefly. For simple
educational reasons, the explanation order does not follow
the numeric order.
For each pin, you will find its name as given
in the literature about the 68000, the name explained plainly and
the description of the pin.
VCC Constant Voltage Current. It's the 68000's power supply pin (5 volts).
GND Ground. It's the ground connection for the 68000.
CLK Clock. Clock signal input.
Note: A BUS is a set of conductors (akin to
a 'bundle' of wires), carrying the same type of information.
A1 to A23 Address. These pins make up the
address bus. We should not confuse these 'A's with the
address registers (A0-A7) that we are studying in
the other courses. Indeed, each of the 'A's
of address registers is coded on 32 bits whereas
here each works only on 1 bit. We are definitely dealing with
a box with wires on which there is or isn't current
(review course 2). One might expect to find
a pin 0, but it is replaced by 2
pins that complete the address bus.
UDS Upper Data Strobe
LDS Lower Data Strobe
With the help of the A1-A23 pins, an address is obtained,
and the UDS and LDS pins signal to the microprocessor whether
to access the high byte, the low byte, or the complete word at that address.
Since each A1-A23 pin can only take on 2 values (0 or 1),
we are in the same situation as with our lamps from course 2.
We had remarked that the number of possibilities was linked to
the number of lamps by the relationship:
possibilities = 2 to the power of the number of lamps.
If we replace lamps with pins, we get as number of
possibilities 2 to the power of 23, which is 8388608. Hence, we can
access 8388608 addresses, each containing not just a byte
but a word, since the microprocessor will then carry out selection
by consulting its UDS and LDS pins. Therefore, we can reach
8388608 words, which is 16777216 bytes, fitting with the 16 megabytes we talked
about in the other courses.
The Data Bus: Same remarks as before. Here, we have 16 pins
(D0 to D15), which of course can only take 2 values, namely 0 or 1. Hence,
the data bus is 16 bits wide and is capable of carrying bytes or words.
It is possible to read as well as write on this bus. It is accessible in
both directions, hence it is bi-directional.
The Control Bus: This group of pins provides additional information.
AS Address Strobe. This pin validates the address found on the address bus.
In plain language, it indicates that everything is OK.
R/W Read-write. Since the data bus is accessible for reading and writing,
this pin indicates which of the two states is active.
UDS, LDS These two pins are part of the Control Bus but we have already
described them above.
DTACK Data Transfer Acknowledge. Indicates that the data transfer is completed.
The Control Bus also includes other commands allowing a good allocation of
buses according to demand.
BR Bus Request. Indicates that another circuit
is asking to take control of the bus.
BG Bus Grant. Signals that the bus will be released.
BGACK Bus Grant Acknowledge. Indicates that another circuit has taken
control of the bus.
Interrupt Control:
IPL Interrupt Pending Level: Three pins of this type IPL0, IPL1,
and IPL2.
Unlike the other pins, these are active when they are at 0. We will return
to the status of these pins in the chapter dealing with the second part of the SR
and interrupts (chapter 4).
System Control:
BERR Bus error. Signals an error in the current execution cycle.
RESET Used to initialize the 68000. However, when a
program executes the RESET instruction, this pin can
go low (0), so that there is re-initialization of external
circuits without affecting the 68000.
HALT Just like the RESET pin, this one is available as
input or output. When it is triggered as an input, the
68000 completes its current bus cycle and then halts.
As output, this pin indicates a double fault
has occurred on a bus. Only RESET can then unlock
the processor.
Processor State:
Three pins (FC2, FC1 and FC0) indicate the state of the
68000.
FC2 FC1 FC0 Type of cycle
0 0 0 reserved (not used)
0 0 1 user data
0 1 0 user program
0 1 1 reserved
1 0 0 reserved
1 0 1 supervisor data
1 1 0 supervisor program
1 1 1 interrupt acknowledgment
You will find many other details about the 68000 in
books such as "Implementing the 68000" by Sybex or in publications by Radio editions.
These details, even if they do not seem crucial, help to
better understand the machine's operating mode, which can
only bring advantages.
Back to ASM_Tutorial